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NVIDIA grants for PhD's
Posted on 3-10-2011 by Cedric Nugteren Tags: GPU

NVIDIA’s Grad Fellowship application is now open. It is a special grant for PhD students working on research that advances parallel computing. The grant is ~25.000 dollars and the deadline is the 8th of December.

Details can be found on their website:

On demand register allocation and deallocation for a multi-threaded processor
Posted on 30-9-2011 by Zhenyu Ye Tags: GPU, architecture

David Tarjan and Kevin Skadron have patented this technique before they published a more advanced technique in ISCA 2011. It is likely that the former technique is in use at the recent generations of GPUs.

Hough Transform on GPU - source code online
Posted on 29-9-2011 by Gert-Jan van den Braak Tags: GPU, CUDA, vision, hough transform

Today we have put the source code of the paper Fast Hough Transform on GPUs: Exploration of Algorithm Trade-Offs (see the Publications page) online. You can find the source code at the Algorithms and tools page page.

Xilinx FPGA Power Estimation Training.
Posted on 9-9-2011 by Shakith Fernando Tags: FPGA, Xilinx

Xilinx is going provide training for power consumption in FPGA. Usually they provide the materials online for free.

Training link

Catapult C HLS
Posted on 8-9-2011 by Shakith Fernando Tags: High Level Synthesis, programming, compiler

A good introductory tutorial for Catapult C

The GPU vs FPGA question..
Posted on 8-9-2011 by Shakith Fernando Tags: GPU, FPGA

This is an interesting paper which is a follow up after today seminar on using FPGA and GPU to accelerate ray tracing algos.

Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration

FPL 2011
Posted on 8-9-2011 by Shakith Fernando Tags: FPGA, conference

FPL 2011 Program is out. This year’s keynote is on using FPGA for acceleration of financial computations. There is a significant trend recently by major financial players to use reconfigurable computing for financial products.

Couple of interesting paper titles.
1. Unifying option-pricing designs for hardware acceleration by Qiwei Jin, David Thomas and Wayne Luk
2. Generic Low-Latency NoC Router Architecture for FPGA Computing Systems by Ye Lu, John McCanny and Sakir Sezer
3. A Radix Tree Router for Scalable FPGA Networks William V. Kritikos, Yamuna Rajasekhar, Andrew G. Schmidt and Ron Sass
4. RAMPSOCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive Mpsoc by Diana Goehringer, Stephan Werner, Michael Huebner and Juergen Becker
5. Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs
Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Raul Torrego and Imanol Martinez
6. High Frequency Trading Acceleration using FPGAs by Christian Leber, Benjamin Geib and Heiner Litz
7. Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System by Michel Kinsy and Michael Pellauer
8. Heterogeneous Platform for Stream Based Applications on FPGAs Jan Kloub, Tomas Mazanec and Antonin Hermanek
9. FPGA Interconnect Architecture Exploration Based on a Statistical Model by Zhen Wang, Ding Xie and Jinmei Lai
10. Resource Management for the Heterogeneous Arrays of Hardware Accelerators by Zdenek Pohl and Milan Tichy
11. A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine by Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada and Tsutomu Yoshinaga

A Programmable Vision Chip Based on Multiple Levels of Parallel Processors
Posted on 6-9-2011 by Gert-Jan van den Braak Tags: vision, architecture

A Programmable Vision Chip Based on Multiple Levels of Parallel Processors, in JSSC Sept. 2011. The architecture can be reconfigured into three architectural templates for different algorithmic patterns, e.g., pixel-parallel, row-parallel, and no-parallel.