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Xilinx releases the Zynq-7000 Extensible Processing Platform
Posted on 1-3-2011 by Zhenyu Ye Tags: FPGA

Xilinx releases its Zynq-7000 Extensible Processing Platform. According to a third party source, the Zynq 7000 is expected to arrive in Q1 2012. The high-end Zynq Z-7040 packs two ARM A9 cores with programmable logic comparable to an XC6VLX240T Virtex6 in an ML605 board.

Simulating 1000 Cores
Posted on 28-2-2011 by Zhenyu Ye Tags: simulator, architecture

There are some related articles on simulating 1000 cores.

Tegra Roadmap
Posted on 16-2-2011 by Zhenyu Ye Tags: GPU

According to the NVIDIA blog, the project KAL-EL will pack four ARM A9 cores into the Tegra.

DAC 2011 Conference Program released.
Posted on 14-2-2011 by Zhenyu Ye Tags: architecture, conference, vision

DAC 2011 conference program is released, with titles of accepted papers. The paper titled “EFFEX: An Embedded Processor for Computer Vision Based Feature Extraction” looks interesting.

Programmable nanowire circuits for nanoprocessors
Posted on 14-2-2011 by Zhenyu Ye Tags: architecture

Programmable nanowire circuits for nanoprocessors, from the Lieber Research Group of Harvard, in Nature 2011. This paper is hitting the news recently. I have not spent any time to read the paper in detail though.

Special Issue on Feature-Oriented Image and Video Computing for Extracting Contexts and Semantics
Posted on 14-2-2011 by Zhenyu Ye Tags: vision

The Journal of Computer Vision and Image Understanding has a Special issue on Feature-Oriented Image and Video Computing for Extracting Contexts and Semantics.

FPGA 2011 workshop
Posted on 14-2-2011 by Zhenyu Ye Tags: GPU, FPGA, vision, OpenCL

The FPGA 2011 has a pre-conference workshop called “The Role of FPGAs in a Converged Future with Heterogeneous Programmable Processors”. In this workshop, Deshanand Singh will talk about Altera’s OpenCL initiative. Altera is hiring people to work on this initiative, which says it “pushes the state-of-the-art in hardware compilation”. According to this description, Altera seems to use the high level synthesis approach like the FCUDA, instead of the many-core template approach advocated by John Wawrzynek. In either way, the frontend of the FPGA toolflow will inevitably shift to OpenCL-like languages. Personally, I prefer the many-core template approach, which use a traditional compiler toolflow for software generation and a processor generator toolflow for hardware generation.

Fast view synthesis using GPU for 3D display, in Transactions on Consumer Electronics 2008. A single view and its depth map are the input for view synthesis.

PPUs, DSE and robotics
Posted on 14-2-2011 by Zhenyu Ye Tags: GPU, architecture, vision

Wikipedia has an entry on physics engine. It is interesting to find some research work on physics processing unit (PPU). However, modern GPU is powerful enough to support the physics engine, which makes a PPU redundant. Will the GPU also make a vision processing unit (VPU) redundant?

An Empirical Architecture-Centric Approach To Microarchitectural Design Space Exploration , to appear in Transactions on Computers. It shows the program-centric analysis is inferior to the architecture-centric analysis. It raises a question to the architecture-independent approach in the workload characterisation community.

Several papers related to vision in the Transactions on Robotics Feb 2011: