Personal page of Roel Jordans
Postdoc
http://www.es.ele.tue.nl/~rjordans
Research interests
I am a PhD student in the Electronic Systems Group of the Electrical Engineering Department at the Eindhoven University of Technology, The Netherlands. My research interests include Design Automation applied to Application Specific Processors and compilation techniques for these platforms. I obtained my MSc degree from Eindhoven University Technology in 2009 and worked on the MAMPS tool flow as a researcher afterwards. As of September 2010 I am involved in the ASAM project as a PhD student under the supervision of prof. dr. H. Corporaal and dr. ir. L. Jozwiak
Teaching activities
- “5SIA0: Embedded Computer Architecture”
- “5LIM0: Parallelization, Compilers, and Platforms”
List of publications
Code generation for reconfigurable explicit datapath architectures with LLVM
Adriaansen, M.; Wijtvliet, M.; Jordans, R.; Waeijen, L. and Corporaal, H., DSD 2016 - 19th Euromicro Conference on Digital System Design, 2016
Link to publication
Tags: compiler, LLVM, CGRA
Instruction-set architecture synthesis for VLIW processors
Roel Jordans, PhD thesis, 2015
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Tags: DSE, VLIW, ASIP, LLVM, software-pipelining
Mixed-Length SIMD Code Generation for VLIW Architectures with Multiple Native Vector-Widths
Erkan Diken, Martin J. O’Riordan, Roel Jordans , Lech Jozwiak, Henk Corporaal and David Moloney, ASAP 2015 - 26th IEEE International Conference on Application-specific Systems, Architectures and Processors, 2015
Link to publication
Tags: compiler, SIMD, Code Generation, VLIW
A high-level implementation of software pipelining in LLVM
Roel Jordans, David Moloney, EuroLLVM 2015, 2015
Link to publication
Tags: VLIW, LLVM, software-pipelining
moviCompile: An LLVM based compiler for heterogeneous SIMD code generation
Erkan Diken, Roel Jordans, Martin J. O’Riordan, LLVM devroom FOSDEM, 2015
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Tags: LLVM
Construction and Exploitation of VLIW ASIPs with Multiple Vector-Widths
Diken, E.; Jordans, R.; Jóźwiak, L. and Corporaal, H., MECO 2014 - 3rd Mediterranean Conference on Embedded Computing, 2014
Tags: VLIW, ASIP, DLP, vectorization
Instruction-set Architecture Exploration of VLIW ASIPs Using a Genetic Algorithm
Jordans, R.; Jóźwiak, L. and Corporaal, H., MECO 2014 - 3rd Mediterranean Conference on Embedded Computing, 2014
Tags: DSE, VLIW, ASIP, genetic algorithm
BuildMaster: Efficient ASIP Architecture Exploration Through Compilation and Simulation Result Caching
Jordans, R.; Diken, E.; Jóźwiak, L. and Corporaal, H., DDECS 2014 - 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2014
Tags: DSE, VLIW, ASIP
Construction and Exploitation of VLIW ASIPs with Heterogeneous Vector-Widths
Diken, E.; Jordans, R.; Corvino, R.; Jóźwiak, L.; Corporaal, H. and Chies, F. A., Microprocessors and Microsystems, 2014
Link to DOI
Tags: VLIW, heterogeneous vectorization, DLP
ASAM: Automatic architecture synthesis and application mapping
Jozwiak, L.; Lindwer, M.; Corvino, R.; Meloni, P.; Micconi, L.; Madsen, J.; Diken, E.; Gangadharan, D.; Jordans, R.; Pomata, S.; Pop, P.; Tuveri, G.; Raffo, L. and Notarangelo, G, Microprocessors and Microsystems, 2013
Link to DOI
Tags: DSE, ASIP, MPSoC
Exploring processor parallelism: Estimation methods and optimization strategies
Roel Jordans, Rosilde Corvino, Lech Jóźwiak, Henk Corporaal, International Journal of Microelectronics and Computer Science, 2013
Link to publication
Tags: VLIW, issue-width estimation, DSE
Exploring Processor Parallelism: Estimation Methods and Optimization Strategies
Roel Jordans, Rosilde Corvino, Lech Jóźwiak, and Henk Corporaal, DDECS - 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2013
Link to publication
Tags: DSE, VLIW, issue-width
Instruction-set Architecture Exploration Strategies for Deeply Clustered VLIW ASIPs
Roel Jordans, Rosilde Corvino, Lech Jóźwiak, and Henk Corporaal, ECyPS - EUROMICRO/IEEE Workshop on Embedded and Cyber-Physical Systems, 2013
Link to publication
Tags: DSE, architecture, VLIW
An Efficient Method for Energy Estimation of Application Specific Instruction-set Processors
Roel Jordans, Rosilde Corvino, Lech Jóźwiak, and Henk Corporaal, DSD - 16th Euromicro Conference on Digital System Design, 2013
Link to publication
Tags: VLIW, Energy estimation
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors
Roel Jordans, Rosilde Corvino, and Lech Jóźwiak, DSD - 15th Euromicro Conference on Digital System Design, 2012
Link to DOI
Tags: DSE, VLIW, issue-width
An automated flow to map throughput constrained applications to a MPSoC
Jordans, R.; Siyoum, F.; Stuijk, S.; Kumar, A. and Corporaal, H., Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011
Link to DOI
Tags: FPGA, DSE, architecture, multi-core