CPU GPU FPGA model memory CUDA DSE application simulator architecture auto-tuning tool compiler vision OpenCL neural networks Xetal hough transform SIMD TTA cluster skeletons High Level Synthesis Augmented Reality power low energy Code Generation Low Power roofline saliency Register File VLIW Huffman Voting Algorithms training optimization Algorithm Classification Memory hierarchy Polyhedral Model low-power SFU Communication Assist Predictable Reconfigurable Architecture visual servoing demo Histogram Energy estimation issue-width multi-core Species scratchpad memory atomic operations loop tiling accelerators Convolutional Neural Networks DVFS cache model issue-width estimation ASIP MPSoC heterogeneous vectorization DLP genetic algorithm vectorization Convolutional Networks Data Reuse Fusion Recomputation Inter-Tile Reuse Temporal Locality High-Level Synthesis wide SIMD explicit datapath thread scheduling Tiling Interchange timing model ultrasound beam forming LLVM synchronizations Spin-lock Dataflow multithreaded machines performance modeling optimization image registration correlation ratio software-pipelining Compilation Software Pipelining cache hash functions GPU register Accelerator Locality ultra-low power Approximate Computing CGRA