Currently available projects are listed below. Please note that project descriptions serve as an indication of interesting topics. Also, everything is open to discuss/change.

Title	Description	Details	Contact
Using GPUs to accelerate the 'cochlea' ear model	The cochlea ear model is developed by INCAS3 in Assen as part of a study on the effects of different types of sounds on humans. This work is on accelerating the 'cochlea' model using GPUs, in particular using the low-power Mali T604 GPU.	PDF (assignment) and PDF (model)	Cedric Nugteren
Architecture exploration for locality optimized accelerators	The goal of this project is to develop and explore hardware accelerator architectures that can effectively run locality optimized tiled versions of vision algorithms. These accelerators should be parameterizable such that different memory hierarchies can be used. Given the iteration ordering the accelerator should maximize parallelism by connecting the PE to the different dimension of the working tile in the iteration order.	PDF	Maurice Peemen
GPU acceleration of the openPSTD code for 3D sound propagation	Simulating acoustic propagation in 3D is a complex, compute intensive and time consuming task. In the acoustics group of the department of the Built Environment (TU/e), an open-source software of the Pseudo-Spectral Time-Domain method (openPSTD) is currently being developed to compute in detail urban sound propagation. The student's task will be to find the most time-consuming parts in the openPSTD code, and accelerate these on one (or multiple) GPUs. The developed GPU code will be integrated in the openPSTD code.	PDF	Gert-Jan van den Braak
Automatic step in sequential C-code parallelization	Automatic extraction of a parallel model from a sequential C-based application specification. The application parallel model will be array-oriented and the extraction of the parallel model will consists in two phases, 1) from C to a polyhedral model and from the polyhedral model to the array-oriented model. This mastership includes cooperation with Compaan company and University of Bourgogne in France.	PDF	Rosilde Corvino
Parallel Computing On Reconfigurable Architectures (multiple topics)	Various projects are available in the field of parallel computing on FPGAs. Focus lies on the domain of computer vision. We will use algorithmic and architecture patterns to program these architectures. Topics include high level synthesis, skeletons, MAMPS.	PDF	Shakith Fernando
Coarse-grained Software Pipelining on Multicore SIMD platforms	Investigate the impact of software pipelining on a coarse-grained level (e.g. tasks) on multicore SIMD architectures such as the CELL and the GPU.	PDF and Slides	Dongrui She
Embedded Mapping of CNNs	Low power implementations of Convolutional Neural Networks are required to support mobile smart vision apps. Explore trade-offs for mapping on various state-of-the-art mobile platforms (TI Panda Board, Nvidia Tegra 2).	Slides	Maurice Peemen
FPGA Neural Network	Develop, test and compare multiple Neural Network Hardware Accelerators. Design of an advanced memory hierarchy to exploit data locality, implementation of a flexible memory controller. Perform performance comparisons with GPU implementations.	Slides	Maurice Peemen
Scale and Rotation Invariance	Expand the current Convolutional Neural Network architectures to support scale and rotation invariant classification of objects. These properties can be yielded by transformation of input images to other representation domains, or by modification of the detection operators.	Slides	Maurice Peemen
Temporal Pattern Classification	Exploring training methods for the classification of actions. Start with the 2d Convolutional Neural Networks and add other mechanisms for classification of temporal patterns. Possibilities are feed-back, FIFO structures, temporal descriptors, motion vectors. Other alternatives that can be used are Hidden Markov Models or Hierarchical Temporal Memory.	Slides	Maurice Peemen
Distributed Renderer for Statically Lit Environments	European Design Centre in 's-Hertogenbosch initiated the iBuild Green project which involves the development of a software tool for configuring and viewing building projects. The iBuild configurator is used for configuring all aspect of a building including buyers options, used materials, kitchen- and bathroom installation, furniture, lighting, etc. It is desirable to present to the potential buyer the future house under different lighting conditions depending on the time of day. Due to limited rendering capacity of desktop- and laptop PCs we seek a distributed solution where the statically lit rooms are rendered as a service and communicated back to the client for viewing.	PDF	Gert-Jan van den Braak

Some specific projects are available. Ask us if you are interested in other projects/companies.

Company	Title	Description	Details	Contact
Vector Fabrics	Modeling performance of parallel C/C++ code	Extending the Pareon compiler front­end based on clang with ability to parse the OpenMP pragmas. Then, you will feed these pragma directives to the modeling engine, which will estimate timing and energy consumption of the parallel application on the target hardware platform. The assignment involves programming in C++ and OCaml. More information in the PDF.	PDF	Henk Corporaal
Assembléon	Development of a training toolset for SMT component recognition	Development and mapping of training tools that are used for component inspection. Assembléon has a new toolflow that can generate a component description from an image. To improve the robustness of the tool-set automated methods for training should be developed. Basic training algorithms are available but these should be improved as well. More information can be found in the PDF.	PDF	Maurice Peemen
Sorama	Mapping sound visualization algorithms for real-time applications	Mapping of the sound and vibration visualization algorithms to different platforms within their real-time specifications. For mapping, multiple platforms can be used based on CPU, GPU or FPGA. Sorama has already developed hardware boards for this task that combine the best of these architectures.	PDF	Maurice Peemen
Prodrive	Master/Traineeship assignment: Vision Guided Motion	The ultimate goal of the Vision Guided Motion trajectory is to perform this assembly fully automated using robotics and computer vision. In cooperation with the students, a series of projects will be formulated (in PARsE, we focus on the architecture side of this project).	PDF	Rob van de Voort
Technolution	High Speed Camera Image Processing on CPU/GPU Platform	Technolution has developed a digital camera assembly that generates up to 40 images per second with dimensions of 4096 x 4096 pixels (14 bits/pixel). Real-time image processing is performed in a number of FPGAs. Is it possible to do this on a CPU/GPU-based platform?	PDF	Henk Corporaal
Technolution	Real-Time Hypervisor Study	What are the limits of the real-time behaviour in multi-core architectures in combination with a real-time hypervisor?	PDF	Henk Corporaal
Broadcom (Sydney)	Mapping of a state of the art 40nm Broadcom WLAN PHY on FPGA	You will be responsible for the mapping of a state of the art 40nm Broadcom WLAN PHY on a Xilinx based FPGA platform. This setup will be essential for fast RTL verification of the PHY and will enable us to do packet error rate testing on FPGA.	Details	Henk Corporaal
Broadcom (Sydney)	Mapping of a state of the art 40nm floating point radio model on FPGA	You will be responsible for the mapping of a state of the art 40nm floating point radio model on a Xilinx based FPGA platform. This setup will be essential for fast RTL verification of the PHY and will enable us to do packet error rate testing on FPGA.	Details	Henk Corporaal