Parallel Architecture Research Eindhoven - PARsE
Welcome to PARsE
Welcome to the website of the parallel architecture research team. The PARsE team is a subdivision of the
Electronic Systems group, part of the
Electrical Engineering departement at
Eindhoven University of Technology (TU/e) in The Netherlands.
Contents of the website
This website contains information on previous, current and future research, education and events. We update the
research log daily with new posts concerning the latest updates in research, discussing articles published at journals and conferences from among others ACM and IEEE. You will find the following sections on the website:
- A daily updated research log.
- An overview of our research, including projects, tools and publications.
- The education page, containing course and student project information.
- Events, such as our GPU symposium.
- More information about us.
Latest research log entries
Cache-aware Roofline model: Upgrading the loft
A paper, titled Cache-aware Roofline model: Upgrading the loft, is to appear in Computer Architecture Letters. The ideas and experiments in this paper are relevant and similar to the ongoing research of PARSE members.
NVIDIA roadmaps updated at GTC 2013
NVIDIA has updated their GPU and Tegra roadmaps at the GPU Technology Conference (GTC), held in the last week of March 2013.
The GPU roadmap includes Volta as the successor of Maxwell, in turn being the successor of the current Kepler architecture. Volta will be NVIDIA’s first 3D stacked GPU, stacking DRAM chips on top of the logic. Using this technology, Volta is said to achieve a bandwidth of 1TB/s.

The Tegra roadmap introduces the Tegra 5 (Logan) and Tegra 6 (Parker) SoCs. Logan will for the first time include a desktop GPU (Kepler architecture), allowing it to run CUDA programs. Parker will feature NVIDIA’s own ARM-based CPU architecture (Denver) and an updated GPU core.

FPGA 2013 Papers on Polyhedral Optimization
The proceeding of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2013 is now available on the ACM Digital Library. There are two papers on polyhedral optimization:
- Polyhedral-based data reuse optimization for configurable computing (doi) (Best Paper Award)
- Improving high level synthesis optimization opportunity through polyhedral transformations (doi)